The present invention is related to the field of electronic circuits. More particularly, the present invention is related to digital signal processing and generating an odd integer division signal from an input reference signal.
A number of situations arise where an output signal is desired that has a period that is based on, and longer than, an input clock signal. Circuits or logic routines that perform this task are often called xe2x80x9cfrequency division circuits,xe2x80x9d or xe2x80x9cdivide-by circuits.xe2x80x9d Division by an even integer is an easily solved problem, and a number of circuit implementations are known. A single clocked register with feedback, for example can perform a divide-by-2 function of an input square wave signal. Division by other even integers can be accomplished with a number of such registers arranged as a shift register, where the output of the shift register can be used for division by powers of two and a combination of outputs from various stages of the shift register can be used for division by even integers that are not powers of 2.
Providing a divide-by function based on an odd integer, however is a much more difficult problem. Conventional division techniques result in a divided output with a non-50 percent duty cycle or are generally limited in terms of the divided signal that they can produce. One of the inventors of the present invention, for example, used a circuit similar to that shown in FIG. 1 in an earlier product sold by another company. This circuit provided a divide-by-three circuit only, and could not perform frequency division for higher odd integers.
From the preceding, it will be seen that there is yet no easily achievable and expandable or flexible circuit for providing a clock signal that is an odd integer division of an input signal.
The present invention provides a method and/or circuit that achieves an expandable, near-50 percent duty cycle, divided-by-N circuit where N is an odd integer.
Using the teachings provided herein, it will be understood by those of skill in the art, that the methods and apparatus of the present invention could be advantageously used in a wide variety of situations requiring odd integer frequency division, such as communication systems, disk-drive controllers or other I/O circuits, general DSP applications, etc.
In particular embodiments, the invention can be understood as comprising a chain or shift register of delay elements having five groups. A first group delay element receives inverted feedback from the fifth group delay element. A second group comprises N chained delay elements, where N is any positive integer greater than or equal to two. A middle group delay element has an inverted clock. A fourth group comprises Nxe2x88x921 chained delay elements. A final group delay element provides the inverted feedback. According to the present invention, the output of the first group and the output of the middle group are combined to provide the divided-by output.
The invention will be better understood with reference to the following drawings and detailed descriptions. In different figures, similarly numbered items are intended to represent similar functions within the scope of the teachings provided herein. In some of the drawings and detailed descriptions below, the present invention is described in terms of the important independent embodiment of a multimedia message system. This should not be taken to limit the invention, which, using the teachings provided herein, can be applied to other data accessing situations.
Furthermore, it is well known in the art that logic systems can include a wide variety of different components and different functions in a modular fashion. Different embodiments of a system can include different mixtures of elements and functions and may group various functions as parts of various elements. For purposes of clarity, the invention is described in terms of systems that include many different innovative components and innovative combinations of components. No inference should be taken to limit the invention to combinations containing all of the innovative components listed in any illustrative embodiment in this specification. All publications, patents, and patent applications cited herein are hereby incorporated by reference in their entirety for all purposes.